This invention generally relates to HDP-CVD deposition processes and more particularly to a method for reducing stress induced defects present in a semiconductor wafer following an HDP-CVD process.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers may be accomplished using various fabrication techniques including oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
As devices become smaller and integration density increases, the high density plasma chemical vapor deposition (HDP-CVD) process has become a key process due to its gap-filling capability. In particular, high density plasma (HDP) processes, such as electron cyclotron resonance (ECR) processes and induced coupling plasma (ICP) processes have been found to produce high-quality silicon dioxide and silicon nitride layers. Generally, HDP-CVD provides a high density of low energy ions resulting in higher quality films at lower deposition temperatures, compared to for example, PECVD. HDP-CVD is particularly ideal for forming interlayer dielectric (ILD) oxide layers because of its superior gap filling capability. Generally, both sputtering and deposition take place simultaneously, resulting in a deposition/sputter ratio (D/S) ratio that may be adjusted according to process parameters. In an HDP-CVD deposition process, for example, a bias power is coupled to the semiconductor wafer to attract ions which sputter (etch) the wafer during deposition (re-sputtering effect), thereby preventing a phenomena known as crowning where the deposition material converges over the trench before an etched feature opening is completely filled with the deposition material. The deposition rate may therefore be more finely tuned to improved CVD deposition properties to, for example, avoid crowning.
The D/S (deposition-sputtering rate ratio) is a commonly used measure of the gap-filling capability of the process. Among the disadvantages of a lower D/S ratio include the possibility of xe2x80x9ccorner clippingxe2x80x9d or xe2x80x9cedge erosionxe2x80x9d along the edges of metal lines and the lowering of processing throughput since it requires a relatively longer period of time to achieve the formation of the HDP-CVD oxide. The high density of the plasma can result in significant heating of the wafer during deposition requiring a cooled wafer chuck to cool the wafer during deposition. Generally, higher sputtering rates (lower D/S ratios) tend to increase the temperature of the wafer substrate and as such high temperatures have been necessary at the early stages of gap filling when low deposition/sputter ratios (typically less than 4) are necessary to fill the high aspect ratio channels. Temperatures as high as 400xc2x0 C. have been observed and at these temperatures significant distortion of the metal features and circuitry have been observed.
On the other hand, a relatively higher D/s ratio results in problems with gap-filling ability leading to the formation of voids. Consequently, many HDP processes according to the prior art have tended to optimize the HDP-CVD process whereby the D/S ratio is carried out at lower levels, for example, about 3.0 and higher temperatures, for example up to about 400xc2x0 C. in a one step process in order to maximize gap-filling ability.
For example, shown in FIG. 1A is a cross-sectional representation of a portion of a multi-level semiconductor device showing metal lines e.g., 12A, 12B, 12C, 12D surrounded by an HDP-CVD deposited oxide 14 forming a inter-level dielectric layer (ILD). One problem with the prior art methods for forming an HDP-CVD ILD has been the build-up of stresses in the semiconductor wafer as HDP-CVD layers are added. Contributing to the stress build-up are thermal mismatches between materials, for example, the HDP-CVD oxide 14 and the metal lines, during HDP-CVD deposition processes carried out at temperatures of, for example up to 400xc2x0 C. During the deposition, variations in temperature may occur prior to, during, or following deposition leading to thermally induced stresses. Conceptually shown in FIG. 1A is a void, e.g., 16 formed in the metal line 12 following a typical HDP-CVD process where the deposition is carried out with one-step process where the deposition is completed primarily at one deposition temperature. For example, it has been found that a one-step HDP-CVD deposition process produces metal void defects e.g., 16, are formed near the metal-oxide interfaces, for example in the sidewall areas e.g., 16B of the metal lines.
Referring to FIG. 1B is shown an exemplary HDP-CVD one step deposition process according to the prior art. In FIG. 1B is shown a portion of a temperature profile during HDP-CVD oxide deposition over a semiconductor wafer substrate according to a typical one step HDP-CVD process. The wafer surface temperature was monitored by a conventional IR sensor during HDP-CVD deposition of HDP oxide in a commercially available Applied Materials Corporation Model Ultima HDP-CVD apparatus. Following the temperature profile shown by data line A, where temperature is indicated on the vertical axis and time on the horizontal axis, the wafer temperature initially rises from a temperature level near 270xc2x0 C. at position 11A to a temperature of near 340xc2x0 C. where it reaches a stable deposition temperature plateau over which deposition takes as indicated around the area indicated at e.g., position 11B. According to this standard HDP-CVD one step deposition procedure of the prior art, temperature differentials of up to about 70xc2x0 C. occur between, for example, the lowest temperature near position 11A and the stable deposition temperature near position 11B. According to this process metal void defects similar to that shown in FIG. 1A at e.g., 16, are present.
As a result of the metal void defects found according to a one step HDP-CVD processing of the prior art, electrical properties and reliability of the metal interconnects is compromised increasing parasitic electrical effects and increasing the probability of device failure due to, for example, electromigration effects.
There is therefore a need in the semiconductor processing art to develop an HDP-CVD process whereby metal void defects are avoided or reduced.
It is therefore an object of the invention to provide an improved HDP-CVD processing method to avoid or reduce the formation of metal void defects while overcoming other shortcomings and deficiencies of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method of reducing stress induced defects in a substrate according to an HDP-CVD process.
In a first embodiment according to the present invention, the method includes providing a substrate for depositing a layer of material according to an HDP-CVD process; igniting a plasma for carrying out an HDP-CVD process; adjusting plasma operating parameters to achieve a first deposition-sputter ratio with respect to the substrate; depositing a first portion of the layer of material according to a first range of substrate temperatures; and, depositing at least a second portion of the layer of material according to at least a second range of substrate temperatures.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.